Memory map detailed

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Thank Lac for the following (with minor edits in order to be more elaborate)
Notice, most of the space is allocated to external devices. The Nintendo 64 doesn't actually have as much space as this map may have you believe. In addition to that, every RCP register (SP to SI) is 1MB in size, but the valid address space of accessible registers is far shorter. All Registers are Read/Write enabled unless specified otherwise, and bits on the left, elaborations on the right!

RDRAM Memory

0x00000000 to 0x03EFFFFF

        0x00000000 to 0x001FFFFF R/W RDRAM range 0 (2MB)
        0x00200000 to 0x003FFFFF R/W RDRAM range 1 (2MB)
        0x00400000 to 0x007FFFFF R/W RDRAM range 2 (4MB) Red Expansion PAK (if installed)
        0x00800000 to 0x03EFFFFF  * Unused

Also note in later revisions of the N64 Motherboard the 2 qty 2 MB chips were changed to a single 4 MB.

        0x00000000 to 0x003FFFFF R/W RDRAM range 0 (4MB)
        0x00400000 to 0x007FFFFF R/W RDRAM range 1 (4MB) Red Expansion PAK (if installed)
        0x00800000 to 0x03EFFFFF  * Unused

RDRAM Registers

0x03F00000 to 0x03FFFFFF

        RDRAM_BASE_REG - 0x03F00000

        0x03F00000 to 0x03F00003 R/W RDRAM_CONFIG_REG or RDRAM_DEVICE_TYPE_REG
        0x03F00004 to 0x03F00007 R/W RDRAM_DEVICE_ID_REG
        0x03F00008 to 0x03F0000B R/W RDRAM_DELAY_REG
        0x03F0000C to 0x03F0000F R/W RDRAM_MODE_REG
        0x03F00010 to 0x03F00013 R/W RDRAM_REF_INTERVAL_REG
        0x03F00014 to 0x03F00017 R/W RDRAM_REF_ROW_REG
        0x03F00018 to 0x03F0001B R/W RDRAM_RAS_INTERVAL_REG
        0x03F0001C to 0x03F0001F R/W RDRAM_MIN_INTERVAL_REG
        0x03F00020 to 0x03F00023 R/W RDRAM_ADDR_SELECT_REG
        0x03F00024 to 0x03F00027 R/W RDRAM_DEVICE_MANUF_REG
        0x03F00028 to 0x03FFFFFF *   Unknown

(SP) Signal Processor Registers

0x04000000 to 0x0400FFFF

        SP_BASE_REG - 0x04040000

        0x04000000 to 0x04000FFF R/W SP_DMEM read/write (4KB)
        0x04001000 to 0x04001FFF R/W SP_IMEM read/write (4KB)
        0x04002000 to 0x0403FFFF *   Unused

        0x04040000 to 0x04040003  SP_MEM_ADDR_REG //Master, SP memory address
           (RW): [11:0] DMEM/IMEM address
                 [12]   0=DMEM,1=IMEM

        0x04040004 to 0x04040007  SP_DRAM_ADDR_REG //Slave, SP DRAM DMA address
           (RW): [23:0] RDRAM address

        0x04040008 to 0x0404000B  SP_RD_LEN_REG //SP read DMA length
           (RW): [11:0] length
                 [19:12] count
                 [31:20] skip                 
                      direction: I/DMEM <- RDRAM

        0x0404000C to 0x0404000F  SP_WR_LEN_REG //SP write DMA length
           (RW): [11:0] length
                 [19:12] count
                 [31:20] skip                 
                      direction: I/DMEM to RDRAM

        0x04040010 to 0x04040013  SP_STATUS_REG //SP status
            (W): [0]  clear halt          (R): [0]  halt
                 [1]  set halt                 [1]  broke
                 [2]  clear broke              [2]  dma busy
                 [3]  clear intr               [3]  dma full
                 [4]  set intr                 [4]  io full
                 [5]  clear sstep              [5]  single step
                 [6]  set sstep                [6]  interrupt on break
                 [7]  clear intr on break      [7]  signal 0 set
                 [8]  set intr on break        [8]  signal 1 set
                 [9]  clear signal 0           [9]  signal 2 set
                 [10] set signal 0             [10] signal 3 set
                 [11] clear signal 1           [11] signal 4 set
                 [12] set signal 1             [12] signal 5 set
                 [13] clear signal 2           [13] signal 6 set
                 [14] set signal 2             [14] signal 7 set
                 [15] clear signal 3
                 [16] set signal 3
                 [17] clear signal 4
                 [18] set signal 4
                 [19] clear signal 5
                 [20] set signal 5
                 [21] clear signal 6
                 [22] set signal 6
                 [23] clear signal 7
                 [24] set signal 7

        0x04040014 to 0x04040017  SP_DMA_FULL_REG //SP DMA full
            (R): [0] valid bit
                     dma full

        0x04040018 to 0x0404001B  SP_DMA_BUSY_REG //SP DMA busy
            (R): [0] valid bit
                     dma busy

        0x0404001C to 0x0404001F  SP_SEMAPHORE_REG //SP semaphore
            (R): [0] semaphore flag (set on read)
            (W): [] clear semaphore flag

        0x04040020 to 0x0407FFFF * Unused

        0x04080000 to 0x04080003  SP_PC_REG //SP PC
           (RW): [11:0] program counter

        0x04080004 to 0x04080007  SP_IBIST_REG //SP IMEM BIST REG
            (W): [0] BIST check           (R): [0] BIST check
                 [1] BIST go                   [1] BIST go
                 [2] BIST clear                [2] BIST done
                                               [3-6] BIST fail
        0x04080008 to 0x040FFFFF * Unused

(DP) Display Processor Command Registers (Rasterizer interface)

0x04100000 to 0x041FFFF

DP Registers detailed

        DPC_BASE_REG - 0x04100000

        0x04100000 to 0x04100003  DPC_START_REG //DP CMD DMA start
           (RW): [23:0] DMEM/RDRAM start address

        0x04100004 to 0x04100007  DPC_END_REG //DP CMD DMA end
           (RW): [23:0] DMEM/RDRAM end address

        0x04100008 to 0x0410000B  DPC_CURRENT_REG //DP CMD DMA end
            (R): [23:0] DMEM/RDRAM current address

        0x0410000C to 0x0410000F  DPC_STATUS_REG //DP CMD status
            (W): [0] clear xbus_dmem_dma  (R): [0]  xbus_dmem_dma
                 [1] set xbus_dmem_dma         [1]  freeze
                 [2] clear freeze              [2]  flush
                 [3] set freeze                [3]  start gclk
                 [4] clear flush               [4]  tmem busy
                 [5] set flush                 [5]  pipe busy
                 [6] clear tmem ctr            [6]  cmd busy
                 [7] clear pipe ctr            [7]  cbuf ready
                 [8] clear cmd ctr             [8]  dma busy
                 [9] clear clock ctr           [9]  end valid
                                               [10] start valid

        0x04100010 to 0x04100013  DPC_CLOCK_REG //DP clock counter
            (R): [23:0] clock counter

        0x04100014 to 0x04100017  DPC_BUFBUSY_REG //DP buffer busy counter
            (R): [23:0] clock counter

        0x04100018 to 0x0410001B  DPC_PIPEBUSY_REG //DP pipe busy counter
            (R): [23:0] clock counter

        0x0410001C to 0x0410001F  DPC_TMEM_REG //DP TMEM load counter
            (R): [23:0] clock counter

        0x0410 0020 to 0x041F FFFF * Unused

(DP) Display Processor Span Registers

0x04200000 to 0x042FFFFF

        DPS_BASE_REG - 0x04200000

        0x04200000 to 0x04200003  DPS_TBIST_REG //DP tmem bist
            (W): [0] BIST check           (R): [0] BIST check
                 [1] BIST go                   [1] BIST go
                 [2] BIST clear                [2] BIST done
                                               [3-10] BIST fail

        0x04200004 to 0x04200007  DPS_TEST_MODE_REG //DP span test mode
           (RW): [0] Span buffer test access enable

        0x04200008 to 0x0420000B  DPS_BUFTEST_ADDR_REG //DP span buffer test address
           (RW): [6:0] bits

        0x0420000C to 0x0420000F  DPS_BUFTEST_DATA_REG //DP span buffer test data
          (RW): [31:0] span buffer data

        0x04200010 to 0x042FFFFF * Unused

MIPS Interface (MI) Registers

0x04300000 to 0x043FFFFF

        MI_BASE_REG - 0x04300000

        0x04300000 to 0x04300003  MI_INIT_MODE_REG or MI_MODE_REG //MI init mode
            (W): [0-6] init length        (R): [0-6] init length
                 [7] clear init mode           [7] init mode
                 [8] set init mode             [8] ebus test mode
                 [9/10] clr/set ebus test mode [9] RDRAM reg mode
                 [11] clear DP interrupt
                 [12] clear RDRAM reg
                 [13] set RDRAM reg mode

        0x04300004 to 0x04300007  MI_VERSION_REG or MI_NOOP_REG //MI version
        Project64 (1.4): 0x02020102
            (R): [7:0] io
                 [15:8] rac
                 [23:16] rdp
                 [31:24] rsp

        0x04300008 to 0x0430000B  MI_INTR_REG //MI interrupt
            (R): [0] SP intr
                 [1] SI intr
                 [2] AI intr
                 [3] VI intr
                 [4] PI intr
                 [5] DP intr

        0x0430000C to 0x0430000F  MI_INTR_MASK_REG //MI interrupt mask
            (W): [0/1] clear/set SP mask  (R): [0] SP intr mask
                 [2/3] clear/set SI mask       [1] SI intr mask
                 [4/5] clear/set AI mask       [2] AI intr mask
                 [6/7] clear/set VI mask       [3] VI intr mask
                 [8/9] clear/set PI mask       [4] PI intr mask
                 [10/11] clear/set DP mask     [5] DP intr mask

        0x04300010 to 0x043FFFFF  Unused

Video Interface (VI) Registers

Video Interface - more in-depth

VI registers do not include services for drawing on the screen which is done to a frame buffer that is passed to the video interface using VI_ORIN_REG. VI registers are for precise control of the Nintendo 64's video output. The registers control hardware setup for timing, color depth as well as resolution among other things. There isn't any room for error when setting them up unless you actually want non-proper video output quality. All registers are listed with their mnemonic first, followed by their offset from the video interface base address.

0x04400000 to 0x044FFFFF


        VI_BASE_REG - 0x04400000

        0x04400000 to 0x04400003  VI_STATUS_REG or VI_CONTROL_REG //VI status/control
           (RW): [1:0] type[0-1] (pixel size) 
                     0: blank (no data, no sync)
                     1: reserved
                     2: 5/5/5/3 ("16" bit)
                     3: 8/8/8/8 (32 bit)
                 [2] gamma_dither_enable (normally on, unless "special effect")
                 [3] gamma_enable (normally on, unless MPEG/JPEG)
                 [4] divot_enable (normally on if antialiased,
                     unless decal lines)
                 [5] reserved - always off
                 [6] serrate (always on if interlaced, off if not)                                          
                 [7] reserved - diagnostics only
                 [9:8] anti-alias (aa) mode[1:0] 
                     0: aa & resamp (always fetch extra lines)                                           
                     1: aa & resamp (fetch extra lines if needed)                                                
                     2: resamp only (treat as all fully covered)                                             
                     3: neither (replicate pixels, no interpolate)                                          
                 [11] reserved - diagnostics only
                 [15:12] reserved

        0x04400004 to 0x04400007  VI_ORIGIN_REG or VI_DRAM_ADDR_REG //VI origin
           (RW): [23:0] frame buffer origin in bytes

        0x04400008 to 0x0440000B  VI_WIDTH_REG or VI_H_WIDTH_REG //VI width 
           (RW): [11:0] frame buffer line width in pixels 
                                        
        0x0440000C to 0x0440000F  VI_INTR_REG or VI_V_INTR_REG //VI vertical intr 
           (RW): [9:0] interrupt when current half-line = V_INTR

        0x04400010 to 0x04400013  VI_CURRENT_REG or VI_V_CURRENT_LINE_REG //VI current vertical line
           (RW): [9:0] current half line, sampled once per line (the lsb of
                       V_CURRENT is constant within a field, and in
                       interlaced modes gives the field number - which is
                       constant for non-interlaced modes)
                       - Writes clears interrupt line

        0x04400014 to 0x04400017  VI_BURST_REG or VI_TIMING_REG //VI video timing 
           (RW): [7:0] horizontal sync width in pixels
                 [15:8] color burst width in pixels
                 [19:16] vertical sync width in half lines
                 [29:20] start of color burst in pixels from h-sync

        0x04400018 to 0x0440001B  VI_V_SYNC_REG //VI vertical sync 
           (RW): [9:0] number of half-lines per field

        0x0440001C to 0x0440001F  VI_H_SYNC_REG //VI horizontal sync
           (RW): [11:0] total duration of a line in 1/4 pixel
                 [20:16] a 5-bit leap pattern used for PAL only (h_sync_period)

        0x04400020 to 0x04400023  VI_LEAP_REG or VI_H_SYNC_LEAP_REG //VI horizontal sync leap
           (RW): [11:0] identical to h_sync_period
                 [27:16] identical to h_sync_period

        0x04400024 to 0x04400027  VI_H_START_REG or VI_H_VIDEO_REG //VI horizontal video
           (RW): [9:0] end of active video in screen pixels
                 [25:16] start of active video in screen pixels

        0x04400028 to 0x0440002B  VI_V_START_REG or VI_V_VIDEO_REG //VI vertical video
           (RW): [9:0] end of active video in screen half-lines
                 [25:16] start of active video in screen half-lines

        0x0440002C to 0x0440002F  VI_V_BURST_REG //VI vertical burst
           (RW): [9:0] end of color burst enable in half-lines
                 [25:16] start of color burst enable in half-lines

        0x04400030 to 0x04400033  VI_X_SCALE_REG //VI x-scale
           (RW): [11:0] 1/horizontal scale up factor (2.10 format)
                 [27:16] horizontal subpixel offset (2.10 format)

        0x04400034 to 0x04400037  VI_Y_SCALE_REG //VI y-scale
           (RW): [11:0] 1/vertical scale up factor (2.10 format)
                 [27:16] vertical subpixel offset (2.10 format)

        0x04400038 to 0x044FFFFF  Unused

Audio Interface (AI) Registers

0x04500000 to 0x045FFFFF
The amount of RDRAM needed by the audio system is dependent on numerous factors. Most importantly, the number of sounds being played at any given time will determine the size of most buffers. Most buffers must be large enough to accommodate the worst case scenario. Applications with fewer voices will need fewer buffers.
Audio Interface - more in-depth

        AI_BASE_REG - 0x04500000

        0x04500000 to 0x04500003  AI_DRAM_ADDR_REG //AI DRAM address
            (W): [23:0] starting RDRAM address (8B-aligned)

        0x04500004 to 0x04500007  AI_LEN_REG //AI length

           (RW): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored
                 [17:0] transfer length (v2.0) - Bottom 3 bits are ignored
        0x04500008 to 0x0450000B  AI_CONTROL_REG //AI control
            (W): [0] DMA enable - if LSB == 1, DMA is enabled

        0x0450000C to 0x0450000F  AI_STATUS_REG //AI status
            (R): [31]/[0] ai_full (addr & len buffer full)
                 [30] ai_busy
                 Note that a 1to0 transition in ai_full will set interrupt
            (W): clear audio interrupt 

        0x04500010 to 0x04500013  AI_DACRATE_REG //AI DAC sample period register
            (W): [13:0] dac rate
                     - vid_clock/(dperiod + 1) is the DAC sample rate
                     - (dperiod + 1) >= 66 * (aclockhp + 1) must be true

        0x04500014 to 0x04500017  AI_BITRATE_REG //AI bit rate
            (W): [3:0] bit rate (abus clock half period register - aclockhp)
                     - vid_clock/(2*(aclockhp + 1)) is the DAC clock rate
                     - The abus clock stops if aclockhp is zero

        0x04500018 to 0x045FFFFF  Unused

Peripheral/Parallel Interface (PI) Registers

0x04600000 to 0x046FFFFF

Data accesses the ROM through the PI registers. More on the Peripheral interface

        PI_BASE_REG - 0x04600000

        0x04600000 to 0x04600003  PI_DRAM_ADDR_REG  //PI DRAM address
           (RW): [23:0] starting RDRAM address

        0x04600004 to 0x04600007  PI_CART_ADDR_REG //PI pbus (cartridge) address
           (RW): [31:0] starting AD16 address

        0x04600008 to 0x0460000B  PI_RD_LEN_REG //PI read length
           (RW): [23:0] read data length

        0x0460000C to 0x0460000F  PI_WR_LEN_REG //PI write length
           (RW): [23:0] write data length

        0x04600010 to 0x04600013 PI_STATUS_REG //PI status
            (R): [0] DMA busy             (W): [0] reset controller
                 [1] IO busy                       (and abort current op)
                 [2] error                     [1] clear intr

        0x04600014 to 0x04600017  PI_BSD_DOM1_LAT_REG or PI_DOMAIN1_REG //PI dom1 latency
           (RW): [7:0] domain 1 device latency

        0x04600018 to 0x0460001B  PI_BSD_DOM1_PWD_REG //PI dom1 pulse width
           (RW): [7:0] domain 1 device R/W strobe pulse width

        0x0460001C to 0x0460001F  PI_BSD_DOM1_PGS_REG //PI dom1 page size
           (RW): [3:0] domain 1 device page size

        0x04600020 to 0x04600023  PI_BSD_DOM1_RLS_REG //PI dom1 release
           (RW): [1:0] domain 1 device R/W release duration

        0x04600024 to 0x04600027  PI_BSD_DOM2_LAT_REG or PI_DOMAIN2_REG //PI dom2 latency
           (RW): [7:0] domain 2 device latency

        0x04600028 to 0x0460002B  PI_BSD_DOM2_PWD_REG //PI dom2 pulse width
           (RW): [7:0] domain 2 device R/W strobe pulse width

        0x0460002C to 0x0460002F  PI_BSD_DOM2_PGS_REG //PI dom2 page size
           (RW): [3:0] domain 2 device page size

        0x04600030 to 0x04600033  PI_BSD_DOM2_RLS_REG //PI dom2 release
           (RW): [1:0] domain 2 device R/W release duration

        0x04600034 to 0x046FFFFF  Unused

RDRAM Interface (RI) Registers

0x04700000 to 0x047FFFFF

        RI_BASE_REG - 0x04700000

        0x04700000 to 0x04700003  RI_MODE_REG //RI mode
           (RW): [1:0] operating mode
                 [2] stop T active
                 [3] stop R active

        0x04700004 to 0x04700007  RI_CONFIG_REG //RI config
           (RW): [5:0] current control input
                 [6] current control enable

        0x04700008 to 0x0470000B  RI_CURRENT_LOAD_REG //RI current load
            (W): [] any write updates current control register

        0x0470000C to 0x0470000F  RI_SELECT_REG //RI select
           (RW): [2:0] receive select
                 [2:0] transmit select

        0x04700010 to 0x04700013  RI_REFRESH_REG or RI_COUNT_REG //RI refresh
           (RW): [7:0] clean refresh delay
                 [15:8] dirty refresh delay
                 [16] refresh bank
                 [17] refresh enable
                 [18] refresh optimize

        0x04700014 to 0x04700017  RI_LATENCY_REG //RI latency
           (RW): [3:0] DMA latency/overlap

        0x04700018 to 0x0470001B  RI_RERROR_REG //RI error
            (R): [0] nack error
                 [1] ack error

        0x0470001C to 0x0470001F  RI_WERROR_REG //RI error
            (W): [] any write clears all error bits

        0x04700020 to 0x047FFFFF  Unused

Serial Interface (SI) Registers

An SI device is a peripheral device, which is connected to the N64 SI (serial port/interface). An SI device is the name for any type of peripheral device that is connected to the joybus, external joybus or joyport, and accessed by the PIF via the serial interface (SI).
0x04800000 to 0x048FFFFF

Detailed (Explaining PIF too!)

SI.gif
        SI_BASE_REG - 0x04800000

        0x04800000 to 0x04800003  SI_DRAM_ADDR_REG
                 SI DRAM address
          (R/W): [23:0] starting RDRAM address
        0x04800004 to 0x04800007  SI_PIF_ADDR_RD64B_REG
                 SI address read 64B
            (W): [] any write causes a 64B DMA write
        0x04800008 to 0x0480000B  Reserved
        0x0480000C to 0x0480000F  Reserved
        0x04800010 to 0x04800013  SI_PIF_ADDR_WR64B_REG
                 SI address write 64B
            (W): [] any write causes a 64B DMA read
        0x04800014 to 0x04800017  Reserved
        0x04800018 to 0x0480001B  SI_STATUS_REG
                 SI status
            (W): [] any write clears interrupt
            (R): [0] DMA busy
                 [1] IO read busy
                 [2] reserved
                 [3] DMA error
                 [12] interrupt
        0x0480001C to 0x048FFFFF  Unused

Unused

0x04900000 to 0x04FFFFFF

          Unused

Cartridge Domain 2(Address 1)

0x05000000 to 0x05FFFFFF

        0x05000000 to 0x05FFFFFF  Cartridge Domain 2
        0x05000508 - some roms read from this address. 
                      SRAM could be here

Cartridge Domain 1(Address 1)

0x06000000 to 0x0FFFFFFF

        0x06000000 to 0x07FFFFFF  Cartridge Domain 1
                                    This address seems to be where
                                    the n64ddrive would be addressed

        0x08000000 to 0x0FFFFFFF  Cartridge Domain 2
                                    SRAM could be here

Cartridge Domain 1(Address 2)

0x10000000 to 0x1000003F ROM header

        0x10000000                 initial PI_BSB_DOM1_LAT_REG value
        0x10000001                 initial PI_BSB_DOM1_PGS_REG value
        0x10000002                 initial PI_BSB_DOM1_PWD_REG value
        0x10000003                 initial PI_BSB_DOM1_PGS_REG value
        0x10000004 to 0x10000007  Clock Rate
        0x10000008 to 0x1000000B  Boot address offset
        0x1000000C to 0x1000000F  Release offset
        0x10000010 to 0x10000013  CRC1
        0x10000014 to 0x10000017  CRC2
        0x10000018 to 0x1000001F  Unused
        0x10000020 to 0x10000033  Image name
        0x10000034 to 0x1000003A  Unused
        0x1000003B                 Manufacturer ID
        0x1000003C to 0x1000003D  Cartridge ID
        0x1000003E                 Country code
        0x1000003F                 Unused

        0x10000040 to 0x10000B6F  RAMROM_BOOTSTRAP_OFFSET
        0x10000B70 to 0x10000FEF  RAMROM_FONTDATA_OFFSET
        0x10000FF0 to 0x10000FFF  Unused
        0x10001000 to 0x10FF9FFF  RAMROM_GAME_OFFSET
        0x10FFA000 to 0x10FFAFFF  RAMROM_APP_READ_ADDR
        0x10FFB000 to 0x10FFBFFF  RAMROM_APP_WRITE_ADDR
        0x10FFC000 to 0x10FFCFFF  RAMROM_RMON_READ_ADDR
        0x10FFD000 to 0x10FFDFFF  RAMROM_RMON_WRITE_ADDR
        0x10FFE000 to 0x10FFEFFF  RAMROM_PRINTF_ADDR
        0x10FFF000 to 0x10FFFFFF  RAMROM_LOG_ADDR
        0x11000000 to 0x17FFFFFF  Unused
        0x18000000 to 0x18000003  GIO Interrupt Register (R)
        0x18000004 to 0x180003FF  Unused
        0x18000400 to 0x18000403  GIO Sync Register (R/W)
        0x18000404 to 0x180007FF  Unused
        0x18000800 to 0x18000803  Cartridge interrupt Register (R)
        0x18000804 to 0x1F39FFFF  Unused

PIF Boot ROM

0x1FC00000 to 0x1FC007BF

        0x1FC00000  PIF_ROM_START
        0x1FC007BF  PIF_ROM_END

PIF (JoyChannel) RAM

0x1FC007C0 to 1FC007FF

        0x1FC007C0  PIF_RAM_START
        0x1FC007C4 (16 low bits)   Status of controller:
            %X  X  X  X  X  X  X  X  X  X  X  X  X  X  X  X
             A  B  Z  ST U  D  L  R  ?  ?  PL PR CU CD CL CR
             A,B,Z,ST    = A,B,Z, Start buttons
             U,D,L,R     = Joypad directions
             ?,?         = Unknown
             PL,PR       = Pan left, Pan right buttons
             CU,CD,CL,CR = C buttons (up,down,left,right)
        0x1FC007FF  PIF_RAM_END

Reserved

0x1FC00800 to 0x1FCFFFFF

          Reserved

Cartridge Domain 1(Address 3)

0x1FD00000 to 0x7FFFFFFF Unknown

external SysAD device

0x80000000 to 0xFFFFFFFF

        0x80000000 to 0x9FFFFFFF  kseg0 (Mirror of 0x00000000 to 0x1FFFFFFF)
        0xA0000000 to 0xBFFFFFFF  kseg1 (Mirror of 0x00000000 to 0x1FFFFFFF)
        0xC0000000 to 0xDFFFFFFF  ksseg (TLB mapped)
        0xE0000000 to 0xFFFFFFFF  kseg3 (TLB mapped)