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It's important to note, and somehow should be "bred into" the sea of information that will soon be here: The o32 ABI that all Nintendo 64 games use is for the R3000 processor!

explain instruction types and their following operations (in a general sense and merely link to the register page for more there information pertaining to them) as well as other misc

Function Field Format

Instruction Formats
(Quick opcode reference sheet)

The exception, COP0 and pseudo instructions aren't in this brief list.
TO-DO: Format into tables - Display C equivalent - Display purpose and description - Practical example - whatever else I'm missing
MIPS instructions are classified into four groups according to their coding formats:

R format

ADD          rd,rs,rt         ADD word
ADDU         rd,rs,rt         Add Unsigned word
AND          rd,rs,rt         AND
DADD         rd,rs,rt         Doubleword ADD
DADDU        rd,rs,rt         Doubleword ADD Unsigned
DDIV         rs,rt            Doubleword DIVide
DDIVU        rs,rt            Doubleword DIVide Unsigned
DIV          rs,rt            DIVide word
DIVU         rs,rt            DIVide Unsigned word
DMULT        rs,rt            Doubleword MULTiply
DMULTU       rs,rt            Doubleword MULTiply Unsigned
DSLL         rd,rt,sa         Doubleword Shift Left Logical
DSLL32       rd,rt,sa         Doubleword Shift Left Logical +32
DSLLV        rd,rt,rs         Doubleword Shift Left Logical Variable
DSRA         rd,rt,sa         Doubleword Shift Right Arithmetic
DSRA32       rd,rt,sa         Doubleword Shift Right Arithmetic +32
DSRAV        rd,rt,rs         Doubleword Shift Right Arithmetic Variable
DSRL         rd,rt,sa         Doubleword Shift Right Logical
DSRL32       rd,rt,sa         Doubleword Shift Right Logical +32
DSRLV        rd,rt,rs         Doubleword Shift Right Logical Variable
DSUB         rd,rs,rt         Doubleword SUBtract
DSUBU        rd,rs,rt         Doubleword SUBtract Unsigned
MFHI         rd               Move From HI register
MFLO         rd               Move From LO register
MTHI         rd               Move To HI register
MTLO         rd               Move To LO register
MULT         rs,rt            MULTiply word
MULTU        rs,rt            MULTiply Unsigned word
NOR          rd,rs,rt         Not OR
OR           rd,rs,rt         OR
SLL          rd,rt,sa         Shift word Left Logical
SLLV         rd,rt,rs         Shift word Left Logical Variable
SLT          rd,rs,rt         Set on Less Than
SLTU         rd,rs,rt         Set on Less Than Unsigned
SRA          rd,rt,sa         Shift word Right Arithmetic
SRAV         rd,rt,rs         Shift word Right Arithmetic Variable
SRL          rd,rt,sa         Shift word Right Logical
SRLV         rd,rt,rs         Shift word Right Logical Variable
SUB          rd,rs,rt         SUBtract word
SUBU         rd,rs,rt         SUBtract Unsigned word
XOR          rd,rs,rt         eXclusive OR

I format

ADDI         rt,rs,imm        ADD Immediate word
ADDIU        rt,rs,imm        Add Immediate Unsigned word
ANDI rt,rs,imm AND Immediate
DADDI        rt,rs,imm        Doubleword ADD Immediate
DADDIU       rt,rs,imm        Doubleword ADD Immediate Unsigned
LUI rt,imm Load Upper Immediate
ORI rt,rs,imm OR Immediate
SLTI         rt,rs,imm        Set on Less Than Immediate
SLTIU        rt,rs,imm        Set on Less Than Immediate Unsigned

LB           rt,offset(base)  Load Byte
LBU          rt,offset(base)  Load Byte Unsigned
LD           rt,offset(base)  Load Doubleword
LDL          rt,offset(base)  Load Doubleword Left
LDR          rt,offset(base)  Load Doubleword Right
LH           rt,offset(base)  Load Halfword
LHU          rt,offset(base)  Load Halfword Unsigned
LL           rt,offset(base)  Load Linked word
LLD          rt,offset(base)  Load Linked Doubleword
LW           rt,offset(base)  Load Word
LWL          rt,offset(base)  Load Word Left
LWR          rt,offset(base)  Load Word Right
LWU          rt,offset(base)  Load Word Unsigned
SB           rt,offset(base)  Store Byte
SC           rt,offset(base)  Store Conditional word
SCD          rt,offset(base)  Store Conditional Doubleword
SD           rt,offset(base)  Store Doubleword
SDL          rt,offset(base)  Store Doubleword Left
SDR          rt,offset(base)  Store Doubleword Right
SH           rt,offset(base)  Store Halfword
SW           rt,offset(base)  Store Word
SWL          rt,offset(base)  Store Word Left
SWR          rt,offset(base)  Store Word Right
SYNC                          SYNChronize shared memory

Load Delay Slot

J format

First of all, I'm well aware that some of the following opcodes fit the criteria for an I-type opcode, but I'd rather group the jump and branch opcodes together.

BEQ          rs,rt,offset     Branch on =
BEQL         rs,rt,offset     Branch on EQual Likely
BGEZ         rs,offset        Branch on >= Zero
BGEZAL       rs,offset        Branch on >= Zero And Link
BGEZALL      rs,offset        Branch on >= Zero And Link Likely
BGEZL        rs,offset        Branch on >= Equal to Zero Likely
BGTZ         rs,offset        Branch on > Zero
BGTZL        rs,offset        Branch on > Zero Likely
BLEZ         rs,offset        Branch on <= Equal to Zero
BLEZL        rs,offset        Branch on <= Zero Likely
BLTZ         rs,offset        Branch on < Zero
BLTZAL       rs,offset        Branch on < Zero And Link
BLTZALL      rs,offset        Branch on < Zero And Link Likely
BLTZL        rs,offset        Branch on < Zero Likely
BNE          rs,rt,offset     Branch on <>
BNEL         rs,rt,offset     Branch on <> Likely
J            target           Jump
JAL          target           Jump And Link
JALR         rs,rd            Jump And Link Register
JR           rs               Jump Register

Jump/Branch Delay Slot

Floating-Point formats

The following instruction function fields are not static and can vary depending on it's purpose. For simplistic reasons, I grouped them like so:

Float R-type

ABS.fmt      fd,fs            floating-point Absolute value
ADD.fmt      fd,fs,ft         floating-point ADD
C.cond.fmt   fs,ft            floating-point floating point Compare
CEIL.L.fmt   fd,fs            floating-point CEILing convert to Long fixed-point
CEIL.W.fmt   fd,fs            floating-point CEILing convert to Word fixed-point
CFC1         rt,fs            Move control word From Floating-Point
CTC1         rt,fs            Move control word To Floating-Point
CVT.D.fmt    fd,fs            floating-point ConVerT to Double floating-point
CVT.L.fmt    fd,fs            floating-point ConVerT to Long fixed-point
CVT.S.fmt    fd,fs            floating-point ConVerT to Single floating-point
CVT.W.fmt    fd,fs            floating-point ConVerT to Word fixed-point
DIV.fmt      fd,fs,ft         floating-point DIVide
DMFC1        rt,fs            Doubleword Move From Floating-Point
DMTC1        rt,fs            Doubleword Move To Floating-Point
FLOOR.L.fmt  fd,fs            floating-point FLOOR convert to Long fixed-point
FLOOR.W.fmt  fd,fs            floating-point FLOOR convert to Word fixed-point
MFC1         rt,fs            Move Word From Floating-Point
MOV.fmt      fd,fs            floating-point MOVe
MTC1         rt,fs            Move Word To Floating-Point
MUL.fmt      fd,fs,ft         floating-point MULtiply
NEG.fmt      fd,fs            floating-point NEGate
ROUND.L.fmt  fd,fs            floating-point ROUND to Long fixed-point
ROUND.W.fmt  fd,fs            floating-point ROUND to Word fixed-point
SQRT.fmt     fd,fs            floating-point SQuare RooT
SUB.fmt      fd,fs,ft         floating-point SUBtract
TRUNC.L.fmt  fd,fs            floating-point TRUNCate to Long fixed-point
TRUNC.W.fmt  fd,fs            floating-point TRUNCate to Word fixed-point

Float I-type

LDC1         ft,offset(base)  Load Doubleword to Floating-Point
LWC1         ft,offset(base)  Load Word to Floating-Point
SDC1         ft,offset(base) Store Doubleword from Floating-Point
SWC1         ft,offset(base) Store Word from Floating-Point

Float B-type

BC1F         offset           Branch on FP False
BC1FL        offset           Branch on FP False Likely
BC1T         offset           Branch on FP True
BC1TL        offset           Branch on FP True Likely

Detailed Opcode List

Arithmetic Logic Unit (ALU)

I'll also sort logical work, etc





Memory Access



Control Flow







Mathemetical Aid

Bitwise Operations

Signedness and Sign Extension