The "interrupt vector table" is a data structure that associates a list of interrupt handlers with a list of interrupt requests. Put simply, an interrupt and exception handler both alter program flow. Interrupts handle external event, e.g. cartridge issue (peripheral interrupt), Pre-nmi (reset type), etc. Exceptions handle instruction faults, e.g. dividing by zero, etc. One thing to note about interrupts and exceptions with the Nintendo 64 that the R4300i architecture doesn't distinguish between them as there's essentially a single handler for them and the two merely have unique masks. However, in applications outside of this situation, they have individual handlers.
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=====Exceptions========= ****Exceptions Reset - External Cold Reset asserted Soft - Reset External Reset asserted NMI - External NMI asserted Machine Check Exception - Internal processor inconsistency EJTAG Debug Address Error - Exception Unaligned memory access or wrong privileges TLB Exceptions - TLB Refill, TLB Invalid, TLB Modified Cache Error Exception - Data error on cache or ecc error on bus during a cache miss Bus Error Exception - Data transfer error Integer Overflow Exception - Trap Exception A trap instruction executed System Call Exception - SYSCALL instruction executed Breakpoint Exception - BREAK instruction executed Reserved Instruction Exception - Invalid or reserved instruction executed Coprocessor Unusable Exception Coprocessor C0 accessed in user mode with CU=0 Coprocessor Ci accessed with CU[i]=0 (i≠0) Floating Point Exception Watch Exception - Access (instruction or data) to a watchpoint a watchpoint is regulated through registers WatchHi and WatchLo in C0 Interrupt Exception - One (or more) interrupt is pending ****Interrupts ++Software interrupts 2 interrupts (0 and 1) Generated by writing in bits IP1 or IP0 in Cause register Masked through bits IM1 and IM0 in Status register ++Hardware interrupts 6 interrupts (from 0 to 5) Generated by: Implementation dependent external lines (0 to 5) Timer or Performance counter interrupt (5) Identified by testing bits IP2 to IP7 in Cause register Masked through bits IM2 to IM7 in Status register =====Behavior===== vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv RESET TYPES RP Reduced power mode (implementation dependent) RE Reverse-endian enables (for user mode) BEV Normal/Bootstrap exception vectors location TS Multiple matches on TLB SR Soft Reset ERL Error Level EXL Exception Level ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Behavior (Reset Exception): Load Config registers with default values Reset registers: Random, Watchpoints, PerfCnts Set Status fields RP <= 0 , BEV <= 1 , TS <= 0 , SR <= 0 , NMI <= 0 , ERL <= 1 Load ErrorEPC Jump to exception vector: 0xBFC0_0000 Behavior (Soft Reset Exception): Reset registers: Watchpoints, PerfCnts Set Status fields RP <= 0 , BEV <= 1 , TS <= 0 , SR <= 1 , NMI <= 0 , ERL <= 1 Load ErrorEPC CP0 register 30 Jump to exception vector: 0xBFC0_0000 Behavior (NMI Exception): Set Status fields RP <= 0 , BEV <= 1 , TS <= 0 , SR <= 0 , NMI <= 1 , ERL <= 1 Load ErrorEPC Jump to exception vector: 0xBFC0_0000 Behavior (Cache error): Set Statusfields ERL <= 1 Load CacheErr( CP0 register 27 (meaning is implementation dependent) Load ErrorEPC Jump to exception vector: 0xBFC0_0200 + 0x100 if BEV=1 0xA000_0000 + 0x100 if BEV=0 Behavior (other exceptions): If not in exception level (i.e., if Status.EXL = 0) Load EPC and Cause.BD If not in branch delay slot: EPC <= PC ; Cause.BD <= 0 If in branch delay slot: EPC <= PC-4 ; Cause.BD <= 1 Load Cause.CE and Cause.ExcCode Cause.CE value is defined only for coprocessor unusable exception Set Status.EXL Load exception specific information into registers Jump to exception vector ________________________________ | | | | | WILL PUT TABLE HERE | | | |________________________________| Interrupt Exceptions Only taken if The pending interrupt is not masked and The global interrupt enable (Status.IE) is set and Status.EXL = 0 and Status.ERL = 0